FPsPIN: An FPGA-based Open-Hardware Research Platform for Processing in the Network
(In Proceedings of the 32nd Annual Symposium on High-Performance Interconnects (HOTI'25), presented in Virtual Event, IEEE Press, Aug. 2025)
Abstract
Network offload offers low-latency communication for use-cases where data-movement needs to be combined with lightweight processing. Processing incoming data on the network hardware instead of the CPU reduces latency (by eliminating the need for the data to be deposited into main memory) and frees CPU cycles. Various methods have been employed to offload protocol- and data-processing onto network interface cards (NICs), from firmware modification to running full Linux on NICs for application execution. The sPIN project enables users to define handlers executed upon packet arrival. While simulations show sPIN’s potential across diverse workloads, a full-system evaluation is lacking. This work presents FPsPIN, a full FPGA-based implementation of sPIN. FPsPIN is showcased through offloaded MPI datatype processing, achieving a 96% overlap ratio. FPsPIN provides an adaptable open-source research platform for researchers to conduct end-to-end experiments on smart NICs.
Documents
download article: download slides:
Recorded talk (best effort)
BibTeX
@article{schneider2025fpspin, author={Timo Schneider and Pengcheng Xu and Torsten Hoefler}, title={{FPsPIN: An FPGA-based Open-Hardware Research Platform for Processing in the Network}}, year={2025}, month={Aug.}, booktitle={Proceedings of the 32nd Annual Symposium on High-Performance Interconnects (HOTI'25)}, location={Virtual Event}, publisher={IEEE Press}, source={http://www.unixer.de/~htor/publications/}, }
