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S. Ramos, T. Hoefler:
	Cache Line Aware Optimizations for ccNUMA Systems (In Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing (HPDC'15) (short paper), presented in Portland, OR, USA, pages 85--88, ACM, ISBN: 978-1-4503-3550-8, Jun. 2015) Abstract Current shared memory systems utilize complex memory hierarchies to maintain scalability when increasing the number of processing units. Although hardware designers aim to hide this complexity from the programmer, ignoring the detailed architectural characteristics can harm performance significantly. We propose to expose the block-based design of caches in parallel computers to middleware designers to allow semi-automatic performance tuning with the systematic translation from algorithms to an analytic performance model. For this, we design a simple interface for cache line aware (CLa) optimization, a translation methodology, and a full performance model for cache line transfers in ccNUMA systems. Algorithms developed using CLa design perform up to 14x better than vendor and open-source libraries, and 2x better than existing ccNUMA optimizations. Documents download article:
	BibTeX
@inproceedings{cla_programming-hpdc15,   author={S. Ramos and T. Hoefler},   title={{Cache Line Aware Optimizations for ccNUMA Systems}},   year={2015},   month={Jun.},   pages={85--88},   booktitle={Proceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing (HPDC'15) (short paper)},   location={Portland, OR, USA},   publisher={ACM},   isbn={978-1-4503-3550-8},   source={http://www.unixer.de/~htor/publications/}, }